Phase-locked loop (PLL) circuits are frequently utilized to lock an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of data sent by a transmitter in the communication system.
A conventional PLL circuit includes a phase detector, a filter and a voltage-controlled oscillator (VCO). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output. The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
Recently, a parallel receiver architecture has become popular in many digital communication systems. The parallel receiver recovers the clock from the incoming data sequence, typically using a PLL circuit. For a detailed discussion of a parallel receiver architecture and clock recovery, respectively, see T. H. Hu, P. R. Gray, "A Monolithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2-.mu.m CMOS," I.E.E.E. J. of Solid-State Circuits, Vol. 28, No. 12, 1314-20 (1993) and J. D. H. Alexander, "Clock Recovery From Random Binary Signals," Electr. Lett., Vol. 11, No. 22, 541-42 (Oct. 1975), each incorporated by reference herein. Generally, the phase detector of a parallel receiver phase-locked loop (PLL) is frequently implemented as a sampled binary phase detector (SBPD).
A potential problem exists, however, for a PLL circuit based on a sampled binary phase detector (SBPD). Specifically, conventional sampled phase detectors generate a continuous charge output signal over the entire clock cycle to minimize the phase difference between the reference signal and the VCO output. The continuous output current, however, introduces an average delay of one-half of the clock cycle between the phase detector and the voltage-controlled oscillator (VCO). This delay significantly contributes to the oscillation of conventional PLL circuits based on sampled phase detectors around a phase error equal to zero (0). Thus, the phase difference between the reference signal and the VCO output never goes to zero and continues to oscillate around zero. Such oscillation may occur in any sampled nonlinear phase detector, where the output signal is constant during a clock cycle. If the oscillation is severe enough, the incoming data signal can be sampled in the wrong bit period. In addition, any amount of oscillation degrades the bit error rate of a receiver.